1. MHz) IEEE 802.11 g 64(20MHz),128(40 MHz) LTE

1.     
Introduction FFT
(Fast Fourier Transform) is one of the algorithms used for DFT (Discrete
Fourier Transform) in the field of DSP (Digital Signal Processing).Due
to enormous development in recent communication system ,OFDM (Orthogonal Frequency
Division Multiplexing ) is one of the modulation technique adapted to reduce
inter-symbol interference (ISI) and inter-carrier interference (ICI) caused by
multi-path effect and improve the channel utilization.FFT is one of the
important application  in OFDM . It is
mainly used in digital video broadcasting-handheld, digital video
broadcasting-terrestrial (DVB-T), audio broadcasting (DAB) ,wireless
communication system, such as IEEE 802.11 standard, cellular communication
(e.g., WiMAX and LTE). This can be used for services such as HDTV, offering increased
capacity for program broadcasting. The various standards are shown in Table
1.11. OFDM General Architecture is shown in Figure 1.1.  Due
to VLSI technology advancement, FFT algorithm can be implemented in single chip
to support various OFDM standards instead of fixed length FFT processor with
little extra hardware cost. Table 1.1 FFT sizes and
sampling rates for various OFDM systems. 

Communication
System

We Will Write a Custom Essay Specifically
For You For Only $13.90/page!


order now

FFT
Size (Sampling Rate)

IEEE 802.11 a

64 (20MHz)

DAB

2048(2MHz),1024(2MHz),512(2MHz),256(2MHz)

DVB-T

8192(8MHz),2048(8MHz)

DVB-H

4096(8MHz)

ADSL

512(2.2MHz)

VDSL

8192(34.5MHz),4096(17.3 MHz),2048(8.6 MHz)
1024(4.3 MHz),512(2.2 MHz)

IEEE 802.11 g

64(20MHz),128(40 MHz)

LTE

3GPPh1 

128(1.6MHz),256(3.4MHz),512(5.7MHz),
1024(11.4MHz),2048(22.8MHz)

 After a brief study of the modern
wireless systems, Tables 1.1 sums up the different parameters required to
design an adaptive FFT architecture for various standards. The word length used
depending on the modulation scheme. It is noted that the wireless standards
transmit data in different channel bandwidths. The sampling rate varies
depending on the channel bandwidth andFFT length. The scope of this thesis
work is to design and implement a reconfigurable FFTArchitecture that
covers various wireless standard using OFDM. 

 1.1  Motivation  The power consumption decreases as the
feature size and the power supply voltage are reduced. However, the power
consumption increases or retains almost the same as the advance of technology.
This reason is the potential workload increase. During the last decade, the
power consumption has become a main constraint in the design of integrated
circuit. In portable applications, low power consumption has long been the main
constraint. Several other factors, for instances, more functionality, higher
workload, and longer operation time, contribute to make the power consumption
and energy efficiency even more critical. The low power techniques gain more
ground due to the steady increasing cost for cooling and packaging. Besides
those Factors, the increasing power consumption has resulted in higher on chip
temperature, which in turn reduces the reliability. The delivery of power
supply to the chip has also raised many problems like power rails design, noise
immunity, IR-drop etc. Therefore the low power techniques are important for the
current and future integrated circuits in particular communication system
design .the motive of this research work
to optimize the dissipation of  FFT
processor with improved performance.        1.2  Problem Description In
recent development of communication system, OFDM is proposed as theprimary
modulation method (Lin et. al, 2005). The FFT and IFFT (Inverse Fast
FourierTransform) of
OFDM sub-blocks are the key components of the system. Thus, FFT plays a significant
role in OFDM system in converting time domain signal to frequency domainrepresentation.
The effectiveness of FFT processor contributes to the optimization of theOFDM system
(Zhong et. al, 2006). Consequently, FFT implementation in embeddedcommunication
system requires complex computation power and low power consumption.Therefore, ASIC
(Application Specific Integrated Circuit) solutions have been widely used to
implement communication systems (Lee et. al, 2004).With the advent of
this DSP application, the study of high performance VLSI (VeryLarge Integrated
Circuit) architecture is increasing in importance (Chang and Nquyen,2006). As
semiconductor technology had moved towards finer size and geometries, both the
available performance and functionality per die increases drastically.
Unfortunately, the power and area consumption of the processors fabricated in
advancing technologies also continues to grow with inefficient algorithm
design. The increasing demand of portable and embedded applications has
contributed significantly to this growing number of power limited
opportunities. Thus, this technology increase has resulted in the current
situation, in which potential FFT application is limited by power and area
consumption. The implementation of Fast Fourier Transform with the modification
of the existing algorithm is brought up as the VLSI technologies improve in
ASIC implementation.The main goal of
this research is to enhance the algorithm and architecturesnecessary for
high performance FFT processors implemented in VLSI semi-customplatform. The
implementation of the enhanced architecture is realized in an ASIC(Application
Specific Integrated Circuit) platform. The highlighted enhancement issupported by a
strong foundation of improvement in power consumption and active chiparea reduction.
A suitable solution achieves the described goal.Power
consumption increase in a standard CMOS VLSI design for FFT application is due
to the complex multiplication within the butterfly design. There are several
methods of computing FFT algorithm in the signal processing in literature which
involves differentnumber of
computation. Concentration is given to FFT computation method
where FFTalgorithm
encompasses many complex multiplication and addition within the butterflyprocessing unit
which significantly consumes power in the FFT processor (Hasan et. al,2003) with large
active chip area consumption.  1.4 Objective and Scope. The prime objective of this research is to explore methods
for robust and efficient communication over different networks. ·        
To develop Low power Multiplier        Design  
Digit Slice Multiplier less multiplier and Implementing it in  FFT design.·        
To develop clock gating Buffer and gray code
counter        Design Controller and Buffer module to
reduce power dissipation by reducing           unwanted switching.·        
To develop High Performance   FFT Processor                    using MDC architecture to improve
throughput and  reduce Power Dissipation.·        
To develop Reconfigurable FFT Architecture1.5 Organization of thesis. Further chapters are organized as: Chapter 2 deals with Literature review Chapter 3 Fast Fourier
transform (FFT) is introduced. We introduce novel methodology to                  Design efficient
parallel-pipelined architectures for FFTcomputation for complex-                    Valued signals are described.Chapter 4 introduces
the design of complex multiplier to reduce power dissipationChapter 5 introduces
the clock gating and improved counter circuit design Chapter 6 introduces
the computation of power spectral density (PSD). A novel low                      ComplexityChapter 7 concludes
with a summary of total contributions of this thesis And
future research                   Directions.Chapter 8 References Chapter 9 Publications2. Literature The Fast Fourier
Transform h2 (FFT) is a very
useful operator that is massively utilized in signal and image processing.
Thus,its hardware implementation has been extensively studied and is still
subject of multiple researches for optimizations.In communication systems, many
applications make use of Orthogonal Frequency Division Multiplexing (OFDM)
modulations such as Digital Terrestrial Television Broadcasting (DTTB), Digital
Audio Broadcasting (DAB), Wireless Local Area Network (WLAN). the OFDM receiver
processes a FFT algorithm depending on the size of the IFFT used by the
transmitter. It then estimates andequalizes
the channel of transmission. The channel estimation also depends on the type of
the guard interval.In a context of large multiplicity of standards, the idea of
combining multiple standards in a unique receiver is growing up. Among the
different demodulation steps previously presented,the FFT operator is one of
the most common operation used. Nevertheless, its hardware consumption is not
negligible.The FFT sizes of the considered OFDM systems are various : 128, 512,
1024, 2048, 3072, 3780, 4096, 8192.In order to develop a multi-standards
receiver, the solution which is generally retained by manufacturers consists in
implementing various Intellectual Properties (IPs) blocks,each associated to a
unique standard. This solution is often under-optimized in the sense that it
does not allow to                                      

 h1variable
length prasad ref

 h2Reconfigurable
Fast Fourier Transform.pdf

 

x

Hi!
I'm Shane!

Would you like to get a custom essay? How about receiving a customized one?

Check it out